Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx™ Virtex FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
FPGAs are increasingly being deployed in various types of applications that span both embedded and general purpose computing. For example, in the embedded domain, FPGAs are being used in applications that range from high-definition video coder/decoders (“codecs”), such as for H.264, through to broadband wireless infrastructure equipment, such as may be used in IEEE 802.16e and Wireless Code-Division Multiple Access (“WCDMA”) applications like Third Generation (“3G”) and Super-3G base stations. In the general purpose computing space, several companies have produced machines equipped with FPGA-accelerator hardware. For example, the Cray XD1 supercomputer employs a parallel arrangement of processors complemented by FPGA-based reconfigurable computing technology. Accordingly, it should be appreciated that FPGAs may be used to realize a diverse set of system functions including: memory controllers to support Double Data Rate (“DDR”), such as DDR2 for example, among other types of memory devices; multi-gigabit serial connectivity; operating embedded software; and realization of complex mathematical calculations.
With respect to complex mathematical calculations conducted by FPGAs, it is desirable to have a substantially complete set of math libraries to support various complex mathematical calculations to be carried out. There are numerous algorithmic options known for evaluating various types of math functions that may be found in a math library associated with general purpose processors and digital signal processors (“DSPs”). Math functions may be evaluated using various implementations of a COordinate Rotation Digital Computer (“CORDIC”) algorithm. As various versions of the CORDIC algorithm are well known, they are not described in unnecessary detail for purposes of clarity. A difficulty associated with implementation of a CORDIC algorithm is determining the number of iterations and quantizations to be used to obtain an output of a target quality of result (“QoR”). While it is possible to over-engineer the implementation of a CORDIC algorithm in order to ensure an acceptable QoR, this over-engineering may consume a significant amount of circuit resources.
Accordingly, it would be both desirable and useful to provide means to determine the number of iterations and quantizations associated with a CORDIC algorithm for a targeted QoR.